Modified source/drain re-oxidation method and system

ABSTRACT

Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, data retention and self align source resistance.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.10/818,564, filed Apr. 6, 2004, which is a continuation of U.S. patentapplication Ser. No. 10/143,450, filed May 10, 2002, now U.S. Pat. No.6,756,268, which is a division of U.S. patent application Ser. No.09/769,162 filed Jan. 24, 2001 (now abandoned).

BACKGROUND OF THE INVENTION

The present invention relates to the field of semiconductor manufactureand, more particularly, to a modified source/drain re-oxidation process.

As computers become increasingly complex, the need for memory storage,and in particular the number of memory cells, increases. At the sametime, there is the need to minimize the size of computers and memorydevices. A goal of memory device fabrication is to increase the numberof memory cells per unit area or wafer area.

Memory devices contain blocks or arrays of memory cells. A memory cellstores one bit of information. Bits are commonly represented by thebinary digits 0 and 1. A conventional non-volatile semiconductor memorydevice in which contents can be electrically programmable orsimultaneously erased by one operation is a flash memory device.

Flash memory devices have the characteristics of low power and fastoperation making them ideal for portable devices. Flash memory iscommonly used in portable devices such as laptop or notebook computers,digital audio players and personal digital assistant (PDA) devices.

In flash memory, a charged floating gate is zero logic state, typicallyrepresented by the binary digit 0, while a non-charged floating gate isthe opposite logic state typically represented by the binary digit 1.Charges are injected or written to a floating gate by any number ofmethods, including avalanche injection, channel injection,Fowler-Nordheim tunneling, and channel hot electron injection, forexample.

The key performance parameters of a flash memory cell are programmingrates, erase rates, and data retention. These parameters are a strongfunction of the post source drain re-oxidation gate edge profile. Thisprofile is also referred to as a reox smile. During source drainre-oxidation, the thickness of the tunnel oxide and oxide-nitride-oxide(ONO) layers are increased along the exposed edge of the gateelectrodes. The profile of this thickness enhancement plays a major rolein the performance of a flash memory cell. As the thickness of thisprofile increases, reliability and data retention increases while eraserates or speeds worsen. Thus, it is desirable to accurately control thethickness of this profile. However, there are only limited ways tomodify this profile. A common way to attempt to modify the profile iscontrolling the conditions of the re-oxidation. The conditionscontrolled are source and drain doping concentration profiles beforeoxidation. However, this approach is limited.

Enhancing the ability to control this source drain re-oxidation gateedge profile is desirable.

SUMMARY OF THE INVENTION

A method that can be used to modify the smile profile during thefabrication of semiconductor devices, such as flash memory, isdisclosed. A memory cell structure is defined on a substrate. A layer ofphosphorous-doped oxide is deposited over substrate. Horizontal surfacesof the layer of phosphorous-doped oxide are selectively removed whilevertical surfaces of the phosphorous-doped oxide remain. The horizontalsurfaces are substantially planar to the substrate surface. The verticalsurfaces are substantially perpendicular to the substrate surface.

A method for fabricating a flash memory cell is disclosed. A self alignsource is formed on a substrate. A drain is formed on the substrate. Alayer of phosphorous-doped oxide is deposited on the substrate. Portionsof the phosphorous-doped oxide layer are removed leaving remainingportions of the phosphorous-doped oxide layer. Standard re-oxidation isperformed on the substrate.

A semiconductor device is disclosed. The semiconductor device includes asubstrate, a drain, a self aligned source, a first oxide layer, a firstpolysilicon layer, a second dielectric layer, a second polysilicon layerand a phosphorous doped oxide layer. The drain is formed in thesubstrate. The self align source is formed in the substrate. The firstoxide layer is deposited in the substrate from the drain to the selfalign source. The first polysilicon layer is deposited over the firstoxide layer. The second dielectric layer is deposited over the firstpolysilicon layer. The second polysilicon layer is deposited over thesecond oxide layer. A phosphorous-doped oxide layer is located onlyalong edges of the first oxide layer, the first polysilicon layer, thesecond oxide layer and the second polysilicon layer.

Other methods and devices are disclosed.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The following detailed description of the present invention can be bestunderstood when read in conjunction with the accompanying drawings,where like structure is indicated with like reference numerals.

FIG. 1 illustrates a semiconductor device for flash memory.

FIG. 2A illustrates a semiconductor device prior to re-oxidation.

FIG. 2B illustrates a semiconductor device after re-oxidation.

FIG. 3A illustrates a portion of a semiconductor device according to oneembodiment of the invention.

FIG. 3B illustrates the portion of the semiconductor device afterre-oxidation according to one embodiment of the invention.

FIG. 4A illustrates standard self aligned source doping after sourceimplant and re-oxidation.

FIG. 4B illustrates self align source doping according to one embodimentof the invention.

FIG. 4C illustrates self align source doping according to one embodimentof the invention.

FIG. 5 illustrates a flash memory device according to one embodiment ofthe invention.

FIG. 6 illustrates a method according to one embodiment of theinvention.

FIG. 7 illustrates a method according to one embodiment of theinvention.

FIG. 8 illustrates a method according to one embodiment of theinvention.

FIG. 9 is a computer system in with which embodiments of the inventionmay be used.

DETAILED DESCRIPTION OF THE INVENTION

For the purposes of describing and defining the present invention,formation of a material “on” a substrate or layer refers to formation incontact with a surface of the substrate or layer. Formation “over” asubstrate or layer refers to formation above or in contact with asurface of the substrate. Formation “in” a substrate or layer refers toformation of at least a portion of a structure in the interior of asubstrate or layer. A “wafer” is a thin, usually round slice ofsemiconductor material, such as silicon, from which chips are made. A“substrate” is the underlying material upon which a device, circuit, orepitaxial layer is fabricated. A “flash memory device” includes aplurality of memory cells. Each “memory cell” of a flash memory devicecan comprise components such as a gate, floating gate, control gate,wordline, channel region, a source, self aligned source and a drain. Aself align source (SAS) is a semiconductor structure that allows anumber of cells to share a common source or source junction. An “anneal”is a high temperature processing step designed to minimize stress in thecrystal structure of the wafer. The term “patterning” refers to one ormore steps that result in the removal of selected portions of layers.The patterning process is also known by the names photomasking, masking,photolithography and microlithography.

FIG. 1 illustrates a semiconductor device 100 for flash memory. FIG. 1is prior art. The device 100 includes a substrate 107, a source 101, adrain 102, a tunnel oxide 103, a first polysilicon (poly) layer 104, adielectric layer 105 and a second poly layer 106.

The substrate 107 is typically comprised of silicon. The source 101 anddrain 102 are formed in the substrate 107 by doping. The source 101 canbe created by doping with As (arsenic) and P (phosphor), individually orin combination. The drain 102 can be formed by doping with As. Thetunnel oxide layer 103 is formed as shown in FIG. 1 and stretches fromthe source 101 to the drain 102. The first poly layer 104 is formed overthe tunnel oxide layer 103. The first poly layer is typically a floatinggate. The first poly layer 104 is typically lightly doped. Thedielectric layer 105 is formed over the first poly layer 104. It can becomposed of a dielectric such as oxide nitride oxide (ONO). The secondpoly layer 106 is formed over the dielectric layer 105. The second polylayer 106 can be comprised of any suitable conductor, but it typicallyis a poly with a metal silicide. The second poly layer 106 can be awordline.

FIG. 2A illustrates a portion of a semiconductor device prior tore-oxidation. FIG. 2A is prior art. A source 201 has already been formedby doping a semiconductor 207. A tunnel oxide layer 202 has been formedover the surface of the semiconductor 207 and a floating gate poly layer203 has been formed over the tunnel oxide layer. The tunnel oxide layer202 is formed to a specific thickness or original thickness 211.

FIG. 2B illustrates the portion of the semiconductor device afterre-oxidation. FIG. 2B is prior art. A re-oxidation oxide profile 208 hasformed as shown in FIG. 2B over surfaces of the device. The re-oxidationoxide profile 208 has two important characteristics or parameters,height 209 and width 210. The height 209 is the vertical distance fromthe top of the source 201 (silicon surface) to the bottom edge of thefloating gate poly layer 203 as shown in FIG. 2B. The width 210 is thehorizontal distance from the edge of the floating gate poly layer 203 tothe point where the tunnel oxide starts getting thicker than theoriginal thickness 211 and the thickness of the rest of the channelregion. The height 209 and width 210 parameters have a large effect onthe operation of the flash memory device. As the height 209 increases,the reliability of the flash memory device increases but erase speeddecreases. As the width 210 increases, erase speed decreases. However,with standard re-oxidation techniques, it is difficult to control theseparameters, 209 and 210, and the re-oxidation profile 208.

FIG. 3A illustrates a portion of a semiconductor device according to oneembodiment of the invention. The portion of the semiconductor deviceincludes a source 301 formed in a semiconductor 307. A tunnel oxidelayer 302 is formed over the surface of the semiconductor 307 and thesurface of the source 301 as shown in FIG. 3A. The floating gate polylayer 303 is formed over the tunnel oxide layer 302. An ONO layer 304 isformed over the floating gate poly layer 303. Another poly layer orwordline poly layer 305 is formed over the ONO layer 304. Thephosphorous doped oxide has been formed over all surfaces of thesemiconductor and removed from all substantially horizontal surfaces sothat the remaining phosphorous doped oxide 306 is only on substantiallyvertical surfaces such as is shown in figure 3A. The phosphorous-dopedoxide can be formed over the semiconductor by using methods such aschemical vapor deposition or spin on glass (SOG). Using the SOG methodcould create higher dopant concentrations. The phosphorous-doped oxidecan be removed from substantially horizontal surfaces by etching suchas, for example, an anisotropic etch.

FIG. 3B illustrates the portion of the semiconductor device afterre-oxidation according to one embodiment of the invention. Are-oxidation oxide profile 308 has formed as shown in FIG. 3B oversurfaces of the device. The re-oxidation oxide profile 308 has twoimportant characteristics or parameters, height 309 and width 310. Theheight 309 is the vertical distance from the top of the source 301(silicon surface) to the bottom edge of the floating gate poly layer 303as shown in FIG. 3B. The width 310 is the horizontal distance from theedge of the floating gate poly layer 303 to the point where the tunneloxide layer 302 starts getting thicker than the original thickness 311and the thickness of the rest of the channel region. The height 309 andwidth 310 parameters have a large effect on the operation of the flashmemory device. As the height 309 increases, the reliability of the flashmemory device increases but erase speed decreases. As the width 310increases, erase speed decreases. However, with standard re-oxidationtechniques, it is difficult to tailor these parameters, 309 and 310, andthe re-oxidation profile 308. By having utilized the phosphor dopedoxide 306, the height 309 is similar to the height of the device ofFIGS. 2A-2C but, the width is significantly less than the width of thedevice in FIGS. 2A-2C. Thus, the data retention of the device in FIG. 3will be similar to the data retention of the device in FIG. 2, but theerase speed of the semiconductor device of figure 3 is likelysignificantly better than the device of FIG. 2. An additional benefit isthat the resistance of the source rail or common source may be lowered.

FIG. 4A illustrates standard self aligned source 400 doping after sourceimplant and re-oxidation. FIG. 4A is prior art. The source doping takesplace at 403. The horizontal surfaces 402 are heavily doped and thevertical surfaces 401 are lightly doped. The resistance of the selfalign source 400 is a function of the dopant atom concentration of alongit. Because of steep profiles formed during shallow trench isolationprocesses, the concentration of dopant atoms along the self align sourceis not uniform. Atoms implanted in the steep slope or vertical surfaces401 have a lower effective concentration due to the nature of theimplant process. This decrease in concentration along the verticalsurfaces 401 of the self align source, leads to higher than expectedself aligned source resistance. This problem increases as the depth ofthe shallow trench increases and this is one of the limiting factors forincreasing the trench depth.

FIG. 4B illustrates self align source 400 doping according to oneembodiment of the invention. FIG. 4B is prior to re-oxidation and aftersource implants 403 and phosphorous doped oxidation 404 and etching.Phosphorous doped oxide has been removed from the horizontal surfaces402 so that the phosphorous doped oxide 404 only remains on the verticalsurfaces 401. FIG. 4C illustrates self align source 400 doping accordingto one embodiment of the invention. FIG. 4C is the self align source ofFIG. 4B after re-oxidation. The vertical surfaces 401 have increaseddoping from phosphorus diffusing out of the phosphorous doped oxide 404.Thus, the vertical surfaces 401 and horizontal surfaces 402 are moreevenly doped than the respective surfaces of FIG. 4A. Furthermore, bysupplying an additional source of dopant directly to the verticalsurfaces 401, the overall self align source resistance can be improved.The rail resistance-limiting factor for trench depth can be greatlyreduced or eliminated. Additionally, the phosphorous doped oxideprevents out-diffusion of phosphorus from regions which are covered bythe phosphorous doped oxide 405 during high temperature thermal cyclingthat follows. The re-oxidation oxide 405 is formed over the phosphorousdoped oxide 404 and horizontal surfaces 402.

FIG. 5 illustrates a flash memory device according to one embodiment ofthe invention. The device is fabricated on a silicon substrate 509. Theself align source 501 is formed in the silicon substrate 509. Thefloating gate layer 504 is formed over the substrate 509. The floatinggate layer 504 typically has a tunnel oxide layer between itself and thesubstrate 509, but the tunnel oxide layer cannot be seen in FIG. 5. AnONO layer is formed over the floating gate layer 504 but is not visiblein FIG. 5. A wordline poly layer 506 is formed under the ONO layer.Field isolation oxide 507 is formed over the wordline poly layer 506.Phosphorous-doped oxide 508 is formed on steep or substantially verticalsurfaces. An example of forming the phosphorous-doped oxide 508 is touse chemical vapor deposition.

The phosphorous-doped oxide 508 is able to modify the source drainre-oxidation process three ways. First, it can act as a dopant sourcewhich allows for adjusting the doping concentration profile 510 from theedge inward for the floating gate poly 504 and from the surface downwardfor the silicon substrate 509. Secondly, the phosphorous doped oxide 508acts as a barrier against phosphorus out-diffusion during hightemperature processing. High temperature processing normally occursduring re-oxidation. Third, the phosphorous doped oxide acts as abarrier against the diffusion of oxygen during re-oxidation processeswhich reduce the lateral oxide encroachment under the floating gatelayer 504.

The oxidation rate of silicon and poly-silicon is dependent on the typeand concentration of the dopant atoms. Generally, the higher theconcentration, the higher the oxidation rate. Additionally, theoxidation rate is dependent on the ability of oxygen and silicon toreact. The greater the distance that these atoms need to diffuse, thelower the oxidation rate. By utilizing the phosphorous-doped oxide, theconcentration profile, edge to center for the floating gate poly can beadjusted and the oxidation rate can be reduced.

The key characteristics of the phosphorous-doped oxide are thickness andphosphor concentration. Some acceptable ranges for thickness is 25 Å to500 Å and the phosphorous concentration is 1% to 6%. The range ofthickness and phosphor concentrations affect the programming rate, eraserate and data retention by assisting (concentration) orreducing(thickness) the oxidation rate in the smile region. Otherdopants besides phosphor can be used in the doped oxide.

FIG. 6 illustrates a method according to one embodiment of theinvention. A memory cell structure is defined on a substrate at block601. The memory cell structure can be all or part of a memory cell. Thememory cell structure can define the dimensions and locations of thememory cell and its components, such as source and drain, on thesubstrate. A source and drain are formed in a semiconductor at block602. The source can be a self align source. A layer of phosphorous-dopedoxide is deposited over the semiconductor at 603. Generally, thephosphorous-doped oxide is deposited over the semiconductor usingchemical vapor deposition. The phosphorous-doped oxide is removed fromsubstantially horizontal surfaces at 604 so that the oxide only remainson substantially vertical surfaces. Normal re-oxidation is performed tofinish fabricating the memory cell.

FIG. 7 illustrates a method of fabricating a flash memory cell accordingto one embodiment of the invention. The dimensions of the flash memorycell are defined at block 701 on a substrate. The source side of theflash cell is blocked at 702. The drain side is implanted with boron-11at 703. The block is then removed from the source side at block 704. Thedrain side is blocked at 705. An oxide dry etch is performed in order toremove isolation oxide along a self align source at block 706. Thesource is implanted with phosphor-31 and arsenic-75 in order to dope theself align source 707. The block is removed from the drain side at 708.A layer of phosphorous-doped oxide is deposited over the flash memorycell at block 709. The thickness of the phosphorous doped oxide and thephosphor concentration of the phosphorous doped oxide are selected toachieve desired characteristics of the flash memory cell, such asprogram rate, erase rate and data retention. For illustrative purposes,some typical thickness and phosphor concentrations are 25 Å to 500 Å and1% to 6%. A directional plasma etch is performed to remove phosphorousdoped oxide from horizontal surfaces at 710. The directional plasma etchselectively leaves the phosphorous doped oxide on only the steep orsubstantially vertical sections of the substrate compared to the planeof the substrate surface. Normal re-oxidation is performed at block 711.

FIG. 8 illustrates a method of fabricating a memory cell according toone embodiment of the invention. The memory cell can be a flash, EPROMor EEPROM type memory cell. A substrate is provided at block 801. Atunnel oxide layer is formed over the substrate at block 802. The tunneloxide layer can be deposited over the substrate. A floating gatepolysilicon layer is formed over the tunnel oxide layer at block 803.The floating gate polysilicon layer is then patterned and etched atblock 804. An ONO layer is formed over the floating gate polysiliconlayer at block 805. A wordline polysilicon layer is formed over the ONOlayer at block 806. The wordline polysilicon layer is then patterned andetched at block 807. The drain is patterned and etched at block 808. Thedrain is implanted with Boron at block 809. The source is patterned atblock 810. The source is then etched at block 811. The source isimplanted with phosphor at block 812. The source is implanted witharsenic at block 813. Phosphor doped oxide is deposited over thepolysilicon layer at block 814. The thickness of the phosphorous-dopedoxide and the phosphor concentration of the phosphorous-doped oxide areselected to achieve desired characteristics of the memory cell, such asprogram rate, erase rate and data retention. For illustrative purposes,some typical thickness and phosphor concentrations are 25 Å to 500 Å and1% to 6%. A directional plasma etch is performed to remove phosphorousdoped oxide from substantially horizontal surfaces at block 815. Asource/drain reoxidation is performed at block 816. The source and drainare implanted with arsenic at block 817. A source and drain anneal isperformed at block 818.

The resulting memory cell will likely have increased erase rates andprogramming rates compared to other conventional memory cells.Furthermore, the resulting memory cell can be fabricated according tomore specific dimensions and parameters.

FIG. 9 is an illustration of a computer system 912 that can use and beused with embodiments of the present invention. As will be appreciatedby those skilled in the art, the computer system 912 would include ROM914, mass memory 916, peripheral devices 918, and I/O devices 920 incommunication with a microprocessor 922 via a data bus 924 or anothersuitable data communication path. The memory devices 914 and 916 can befabricated according to the various embodiments of the presentinvention. ROM 914 can include EPROM, EEPROM, or flash memory. Massmemory 916 can include DRAM, synchronous RAM or flash memory.

Many other electronic devices can be fabricated utilizing variousembodiments of the present invention. For example, memory devicesaccording to embodiments of the invention can be used in electronicdevices such as cell phones, digital cameras, digital video cameras,digital audio players, cable television set top boxes, digital satellitereceivers, personal digital assistants and the like.

Having described the invention in detail and by reference to preferredembodiments thereof, it will be apparent that modifications andvariations are possible without departing from the scope of theinvention defined in the appended claims. Other suitable materials maybe substituted for those specifically recited herein. For example, thesubstrate may be composed of semiconductors such as gallium arsenide orgermanium. Additionally, other dopants may be utilized besides thosespecifically stated. Generally, dopants are found in groups III and V ofthe periodic table.

1. A method of memory cells comprising: defining a dimension of a flashcell on a substrate utilizing photolithography and plasma etching toprovide steep walls in the substrate; fabricating a drain in a drainregion of the substrate by: blocking a source region of the flash cell;implanting arsenic; and removing blocking from the source region;fabricating a self aligned source in the source region of the substrateby: blocking the drain region of the flash cell; performing an oxide dryetch in order to remove isolation oxide along the self aligned sourceregion; implanting phosphorous to dope the self aligned source;implanting arsenic to dope the self aligned source; and removingblocking from the drain region of the flash cell; selecting at least anerase rate by a desired thickness and a desired phosphorousconcentration of a phosphorous doped oxide layer; using chemical vapordeposition to provide the phosphorous doped oxide layer having thedesired thickness and the desired phosphorous concentration over and inplaces, in contact with the substrate; performing a directional plasmaetch on the phosphorous doped oxide layer to form sidewalls in contactwith both the substrate and the steep walls; and performing re-oxidationon the substrate to form a desired oxide profile width in the selfaligned source region adjacent the steep walls which is less than awidth of an oxide profile that can be provided in the absence of thephosphorous doped oxide sidewalls.
 2. A method of fabricating memorycells comprising: doping a drain region in a substrate with a firstdopant; doping a source region in the substrate with a second dopant;depositing a doped oxide layer over the substrate according to a desiredthickness and a desired phosphorus concentration used to provide atleast a desired erasure rate; selectively removing horizontal portionsof the doped oxide layer while leaving steep portions along steepexposed side-walls; and performing re-oxidization on the substrate toprovide a desired oxide profile width which is less than an oxideprofile width that can be provided in the absence of the doped oxidelayer.
 3. The method of claim 2, wherein a thickness of the doped oxidelayer is in the range of 25 Å to 500 Å.
 4. The method of claim 2,wherein said phosphorous concentration is in the range of about 1% toabout 6%.
 5. A method of fabricating memory cells comprising: providinga substrate having a memory cell; doping one or more horizontal surfacesof said memory cell to a first dopant concentration; doping one or morevertical surfaces of said memory cell coupled to said one or morehorizontal surfaces to a second dopant concentration, said second dopantconcentration being lower than said first dopant concentration; andforming one or more phosphorous doped oxide sidewalls horizontally incontact with said substrate and vertically in contact with said one ormore vertical surfaces of said memory cell, said one or more verticalphosphorous doped oxide sidewalls having an additional dopantconcentration.
 6. The method of claim 5, wherein said additional dopantconcentration and said second dopant concentration produce an effectivedopant concentration.
 7. The method of claim 5, wherein said effectivedopant concentration is substantially equal to the first dopantconcentration.
 8. The method of claim 5, wherein the additional dopantconcentration, the second dopant concentration, and the first dopantconcentration are selected to provide a desired resistance.
 9. Themethod of claim 5 further comprising subjecting said substrate tore-oxidation.
 10. The method of claim 5 further comprising etching saidsubstrate.
 11. The method of claim 5, wherein said doping is prior tosaid re-oxidation.
 12. The method of claim 5, wherein said re-oxidationincreases doping in said one or more vertical surfaces from phosphorusdiffusing out of said one or more phosphorous doped oxide sidewalls. 13.The method of claim 5, wherein said re-oxidation forms a re-oxidationoxide layer over said one or more phosphorous doped oxide sidewalls andsaid one or more horizontal surfaces.
 14. The method of claim 5, whereinsaid re-oxidation is accomplished by thermal re-oxidation.
 15. Themethod of claim 5, wherein said sidewalls is formed by providing aphosphorous doped oxide layer having a thickness in the range of about25 Å to about 500 Å, and etching said phosphorous doped oxide layer. 16.The method of claim 5, wherein said additional dopant concentration is aphosphorous concentration from about 1% to about 6%.
 17. A method offabricating memory cells comprising: providing a substrate; forming aself align source having one or more horizontal surfaces substantiallyplanar to the substrate with a first dopant concentration, one or morevertical surfaces substantially perpendicular and coupled to the one ormore horizontal surfaces with a second dopant concentration, said seconddopant concentration being lower than said first dopant concentration,and a first one or more substantially vertical phosphorous doped oxidelayers formed over the one or more vertical surfaces; forming a tunneloxide layer over at least a portion of the self aligned source; forminga floating gate layer over at least a portion of said tunnel oxidelayer; forming a dielectric layer over at least a portion of saidfloating gate layer; forming a wordline poly layer over at least aportion of said dielectric layer; forming a fielding isolation oxidelayer over at least a portion of said wordline poly layer; patterningone or more of the formed layers to from substantially verticalsurfaces; and forming a second one or more substantially verticalphosphorous doped oxide layers vertically in contact with saidsubstantially vertical surfaces and horizontally in contact with saidsubstrate, said first and second one or more substantially verticalphosphorous doped oxide layers having an additional dopantconcentration.
 18. The method of claim 17, wherein said substantiallyvertical phosphorous doped oxide layers have a thickness in the range ofabout 25 Å to about 500 Å.
 19. The method of claim 17, wherein saidadditional dopant concentration is a phosphorous concentration fromabout 1% to about 6%.
 20. The method of claim 17, wherein saidadditional dopant concentration and said second dopant concentrationproduce an effective dopant concentration.
 21. The method of claim 17,wherein said effective dopant concentration is substantially equal tothe first dopant concentration.
 22. The method of claim 17, wherein theadditional dopant concentration, the second dopant concentration, andthe first dopant concentration are selected to provide a desiredresistance.
 23. The method of claim 17 further comprising subjectingsaid substrate to re-oxidation.
 24. The method of claim 17 furthercomprising etching said substrate.
 25. The method of claim 17 furthercomprising utilizing shallow trench isolation.
 26. The method of claim17, wherein the floating gate layer is a lightly doped polysiliconlayer.
 27. The method of claim 17, wherein the dielectric layer is anoxide-nitride-oxide.
 28. The method of claim 17, wherein the wordlinelayer is a polysilicon with a metal silicide.
 29. The method of claim17, wherein said substrate is selected from silicon, gallium arsenide,germanium, and combination thereof.
 30. The method of claim 17 furthercomprising performing a source/drain anneal.
 31. The method of claim 17,wherein forming includes depositing, doping, and patterning one or moresaid formed layers, wherein individually said first, second, andadditional dopant concentrations is for a material selected fromarsenic, boron, phosphor, an element from Group III and V of theperiodic table, and combinations thereof.
 32. The method of claim 17,wherein said depositing is by chemical vapor deposition or spin onglass.